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rtl
esl synthesis
21,213,375 websites (safe search)
Esterel EDA
ESL-to-RTL synthesis for control-intensive IP design and verification.
RTL
VHDL
Verilog
code generation
SystemC
formal methods
correct by construction
ESL synthesis
automated implementation
Electronic System Level
unambiguous specifications
Esterel Studio
www.esterel-eda.com - 2009-02-09
Welcome to Sequence Design - Enabling Power-Aware Nanometer SoCs
Power-aware SoC design with products for RTL power,Signal Integrity,ESL,concurrent physical optimization of leakage power,MTCMOS power gating & multi-Vt,active ...
power
optimization
analysis
post
pre
active
dynamic
physical
ESL
drop
voltage
static
RTL
synthesis
concurrent
power reduction
Signal Integrity analysis
ESL synthesis
power optimization
Clock power
ESL Power analysis
ESL simulation
leakage power analysis
low power design & analysis
MTCMOS power gating
physical power closure
power estimation
power grid analysis
power integrity analysis
RLC extraction
Voltage aware timing
www.low-power-design.com - 2009-02-04
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